Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". Quad: Must be connected to same signal as pin 3 IO1/DO to guarantee correct operation for temporary single mode transfers during QSPI mode.
Input of programmer, used to receive data from the target SPI.
Output of programmer, used to transmit data to the target SPI. They can be left open or connected to GND. *On later J-Link products like the J-Link ULTRA, these pins are reserved for firmware extension purposes. They should also be connected to GND in the target system. Pins 4, 6, 8, 10, 12 are GND pins connected to GND in J-Link. Older J-Links may not be able to supply power on this pin. This pin can be used to supply power to the target hardware. Typically connected to the reset pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". Input of J-Link, used to receive data from the target SPI. Output of J-Link, used to transmit data to the target SPI.ĭata-out of target SPI. It is normally fed from Vdd of the target board and must not have a series resistor.ĭata-input of target SPI. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target.
0 kommentar(er)
